View V437216C04VDTG-75_5119372.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mosel vitelic 1 V437216C04VDTG-75 3.3 volt 16m x 72 high performance pc133 register pll ecc sdram module preliminary V437216C04VDTG-75 rev. 1.2 july 2001 features 168 pin registered ecc 16,777,216 x 72 bit oganization sdram modules utilizes high performance 16m x 4 sdram in tsopii-54 packages fully pc board layout compatible to intel? rev 1.2 module specification single +3.3v (?0.3v) power supply programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs, outputs are lvttl compatible 4096 refresh cycles every 64 ms serial present detect (spd) description the V437216C04VDTG-75 memory module is organized 16,777,216 x 72 bits in a 168 pin dual in line memory module (dimm). the 16m x 72 registered dimm uses 18 mosel-vitelic 16m x 4 ecc sdram. the x72 registered modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. sdram performance module frequency vs ac parameter key component timing parameters -7 units t ck clock frequency (max.) 143 mhz t ac clock access time cas latency = 3 5.4 ns frequency cl (cas latency) t rcd t rp t rc unit V437216C04VDTG-75 133 mhz (pc) 3 338clk
2 V437216C04VDTG-75 rev. 1.2 july 2001 mosel vitelic V437216C04VDTG-75 pin configurations (front side/back side) notes: * these pins are not used in this module. pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vss i/o1 i/o2 i/o3 i/o4 vcc i/o5 i/o6 i/o7 i/o8 i/o9 vss i/o10 i/o11 i/o12 i/o13 i/o14 vcc i/o15 i/o16 cbo cb1 vss nc nc vcc we dqm0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 dqm1 cs0 du vss a0 a2 a4 a6 a8 a10(ap) ba1 vcc vcc clk0 vss du cs2 dqm2 dqm3 du vcc nc nc cb2 cb3 vss i/o17 i/o18 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 i/o19 i/o20 vcc i/o21 nc du cke1* vss i/o22 i/o23 i/o24 vss i/o25 i/o26 i/o27 i/o28 vcc i/o29 i/o30 i/o31 i/o32 vss clk2* nc wp sda scl vcc 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 vss i/o33 i/o34 i/o35 i/o36 vcc i/o37 i/o38 i/o39 i/o40 i/o41 vss i/o42 i/o43 i/o44 i/o45 i/o46 vcc i/o47 i/o48 cb4 cb5 vss nc nc vcc cas dqm4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 dqm5 cs1 ras vss a1 a3 a5 a7 a9 ba0 a11 vcc clk1* a12 vss cke0 cs3 dqm6 dqm7 du vcc nc nc cb6 cb7 vss i/o49 i/o50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 i/o51 i/o52 vcc i/o53 nc du rege vss i/o54 i/o55 i/o56 vss i/o57 i/o58 i/o59 i/o60 vcc i/o61 i/o62 i/o63 i/o64 vss clk3* nc sa0 sa1 sa2 vcc pin names a0?11 address inputs i/o1?/o64 data inputs/outputs ras row address strobe cas column address strobe we read/write input ba0, ba1 bank selects cke0 clock enable cs 0 , cs 2 chip select clk0?lk3 clock input dqm0?qm7 data mask vcc power (+3.3 volts) vss ground scl clock for presence detect sda serial data out for presence detect sa0?2 serial data in for presence detect cb0?b4 check bits (x72 organization) nc no connection rege register enable du don? use
mosel vitelic V437216C04VDTG-75 3 V437216C04VDTG-75 rev. 1.2 july 2001 module part number information block diagram sdram 3.3v 4 mosel-vitelic manufactured v 168 pin registered dimm x 4 component c refresh rate 4k 0 3 depth 16 4 banks 4 tsop width 72 lvttl v d version d gold g75 - -75 pc133 3-3-3 t rqm0 i/o1 i/o4 10 ? rcs0 cs d0 d17 ras r e g i s t e r v dd rras d0 d17 cas rcas d0 d17 we rwe cke0 r0cke0, r1cke0 dqm0 dqm7 rdqm0 rdqm7 cs0, cs rc0, rcs2 d0 d17 a0 a11 ra0 ra11 d0 d17 ba0, ba1 pll clk pll rba0, rba1 clk1 clk3 rege d0 d17 12pf 10k 10k dqm i/o1 i/o4 d0 i/o5 i/o8 10 ? cs dqm i/o1 i/o4 d1 rqm4 i/o33 i/o36 10 ? cs dqm i/o1 i/o4 d9 i/o37 i/o40 10 ? cs dqm i/o1 i/o4 d10 rqm1 i/o9 i/o12 10 ? cs dqm i/o1 i/o4 d2 i/o13 i/o16 10 ? cs dqm i/o1 i/o4 d3 rqm5 i/o41 i/o44 10 ? cs rqm2 i/o17 i/o20 10 ? cs dqm i/o1 i/o4 d5 i/o21 i/o24 10 ? cs dqm i/o1 i/o4 d6 rqm6 i/o49 i/o52 10 ? cs dqm i/o1 i/o4 d14 i/o53 i/o56 10 ? cs dqm i/o1 i/o4 d15 rqm3 i/o25 i/o28 10 ? cs dqm i/o1 i/o4 d7 i/o29 i/o32 10 ? cs dqm i/o1 i/o4 d8 rqm7 i/o57 i/o60 10 ? cs dqm i/o1 i/o4 d16 i/o61 i/o64 10 ? cs dqm i/o1 i/o4 d17 dqm i/o1 i/o4 d11 i/o45 i/o48 10 ? cs dqm i/o1 i/o4 d12 cb1 cb3 10 ? cs dqm i/o1 i/o4 d4 cb4 cb7 10 ? cs dqm i/o1 i/o4 d13 rcs2 clk0 12pf 10k
4 V437216C04VDTG-75 rev. 1.2 july 2001 mosel vitelic V437216C04VDTG-75 serial presence detect information a serial presence detect storage device e 2 prom is assembled onto the module. informa- tion about the module configuration, speed, etc. is written into the e 2 prom device during module pro- duction using a serial presence detect protocol (i 2 c synchronous 2-wire bus) spd-table for 75 modules: byte number function described spd entry value hex value 16mx72 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12 0c 4 number of column addresses (for x4 sdram) 10 0a 5 number of dimm banks 1 01 6 module data width 72 48 7 module data width (continued) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 7.5 ns 75 10 sdram access time from clock at cl=3 5.4 ns 54 11 dimm config (error det/corr.) ecc 02 12 refresh rate/type self-refresh, 15.8 s80 13 sdram width, primary x4 04 14 error checking sdram data width n/a / x4 04 15 minimum clock delay from back to back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4, 8, full page 8f 17 number of sdram banks 4 04 18 supported cas latencies cl = 3 04 19 cs latencies cs latency = 0 01 20 we latencies wl = 0 01 21 sdram dimm module attributes registered/buffered 1f 22 sdram device attributes: general vcc tol 10% 0e 23 minimum clock cycle time at cas latency = 2 not supported 00 24 maximum data access time from clock for cl = 2 not supported 00 25 minimum clock cycle time at cl = 1 not supported 00 26 maximum data access time from clock at cl = 1 not supported 00 27 minimum row precharge time 20 ns 14 28 minimum row active to row active delay t rrd 15 ns 0f 29 minimum ras to cas delay t rcd 20 ns 14 30 minimum ras pulse width t ras 45 ns 2d
mosel vitelic V437216C04VDTG-75 5 V437216C04VDTG-75 rev. 1.2 july 2001 dc characteristics t a = 0 c to 70 c; v ss = 0 v; v dd , v ddq = 3.3v 0.3v 31 module bank density (per bank) 128 mbyte 20 32 sdram input setup time 1.5 ns 15 33 sdram input hold time 0.8 ns 08 34 sdram data input setup time 1.5 ns 15 35 sdram data input hold time 0.8 ns 08 62-61 superset information (may be used in future) 00 62 spd revision revision 2 02 63 checksum for bytes 0 - 62 c6 64 manufacturer s jedec id code mosel vitelic 40 65-71 manufacturer s jedec id code (cont.) 00 72 manufacturing location 73-90 module part number (ascii) V437216C04VDTG-75 91-92 pcb identification code 93 assembly manufacturing date (year) 94 assembly manufacturing date (week) 95-98 assembly serial number 99-125 reserved 00 126 intel specification for frequency 64 127 reserved 8d 128+ unused storage location 00 symbol parameter limit values unit min. max. v ih input high voltage 2.0 v cc +0.3 v v il input low voltage 0.3 0.8 v v oh output high voltage (i out = 4.0 ma) 2.4 v v ol output low voltage (i out = 4.0 ma) 0.4 v i i(l) input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0v) 10 10 a i o(l) output leakage current (dq is disabled, 0v < v out < v cc ) 10 10 a spd-table for 75 modules: (continued) byte number function described spd entry value hex value 16mx72
6 V437216C04VDTG-75 rev. 1.2 july 2001 mosel vitelic V437216C04VDTG-75 capacitance t a = 0 c to 70 c; v dd = 3.3v 0.3v, f = 1 mhz absolute maximum ratings symbol parameter limit values unit c i1 input capacitance (a0 to a11, ras , cas , we )15pf c i2 input capacitance (cs0 -cs3 )15pf c icl input capacitance (clk0) 20 pf c i3 input capacitance (cke0) 15 pf c i4 input capacitance (dqm0-dqm7) 15 pf c io input/output capacitance (i/o1-i/064) 16 pf c sc input capacitance (scl, sa0-2) 8 pf c sd input/output capacitance 18 pf parameter max. units voltage on vdd supply relative to v ss -1 to 4.6 v voltage on input relative to v ss -1 to 4.6 v operating temperature 0 to +70 c storage temperature -55 to 125 c power dissipation 9w
mosel vitelic V437216C04VDTG-75 7 V437216C04VDTG-75 rev. 1.2 july 2001 standby and refresh currents 1 t a = 0 c to 70 c, v cc = 3.3v 0.3v symbol parameter test conditions 16m x 72 unit note i cc 1 operating current burst length = 4, cl = 3 t rc > = t rc (min), t ck > = t ck (min), io = 0 ma 2 bank interleave operation 2700 ma 1,2 i cc 2p precharged standby current in power down mode cke< = v il (max), t ck > = t ck (min) 36 ma i cc 2n precharged standby current in non-power down mode cke> = v ih (min), t ck > = t ck (min), input changed once in 3 cycles 810 ma cs = high i cc 3p active standby current in power down mode cke< = v il (max), t ck > = t ck (min) 144 ma i cc 3n active standby current in non-power down mode cke> = v ih (min), t ck > = t ck (min), input changed one time 990 ma cs = high i cc 4 burst operating current t rc = infinite, cl = 3, t ck > = t ck (min), io = 0 ma 2 banks activated 2160 ma 1, 2 i cc 5 auto refresh current t rc >= t rc (min) 2700 ma 1,2 i cc 6 self refresh current cke = <0,2 v standard 18 ma 1,2 l-version 7.2
8 V437216C04VDTG-75 rev. 1.2 july 2001 mosel vitelic V437216C04VDTG-75 ac characteristics 3,4 t a = 0 to 70 c; v ss = 0v; v cc = 3.3v 0.3v, t t = 1 ns # symbol parameter limit values unit note -75 min. max. clock and clock enable 1t ck clock cycle time cas latency = 3 cas latency = 2 7.5 10 ns ns 2f ck system frequency cas latency = 3 cas latency = 2 133 100 mhz mhz 3t ac clock access time cas latency = 3 cas latency = 2 5.4 6 ns ns 4,5 4t ch clock high pulse width 2.5 ns 6 5t cl clock low pulse width 2.5 ns 6 6t cs input setup time 1.5 ns 7 7t ch input hold time 0.8 ns 7 8t cksp cke setup time (power down mode) 2.5 ns 8 9t cksr cke setup time (self refresh exit) 8 ns 9 10 t t transition time (rise and fall) 0.3 1.2 ns common parameters 11 t rcd ras to cas delay 20 ns 6 12 t rc cycle time 60 ns 6 13 t ras active command period 45 100k ns 6 14 t rp precharge time 20 ns 6 15 t rrd bank to bank delay time 15 ns 6 16 t ccd cas to cas delay time (same bank) 1 clk refresh cycle 17 t srex self refresh exit time 10 ns 18 t ref refresh period (8192 cycles) 64 ms read cycle 19 t oh data out hold time 3 ns 2 20 t lz data out to low impedance time 1 ns 21 t hz data out to high impedance time 3 7 ns 7 22 t dqz dqm data out disable latency 2 clk write cycle 23 t dpl data input to precharge (write recovery) 2 clk 24 t dqw dqm write mask latency 0 clk
mosel vitelic V437216C04VDTG-75 9 V437216C04VDTG-75 rev. 1.2 july 2001 notes: 1. the specified values are valid when addresses are changed no more than once during t ck (min.) and when no operation commands are registered on every rising clock edge during t rc (min). values are shown per module bank. 2. the specified values are valid when data inputs (dq s) are stable during t rc (min.). 3. all ac characteristics are shown for device level. an initial pause of 100 s is required after power-up, then a precharge all banks command must be given followed by 8 auto refresh (cbr) cycles before the mode register set operation can begin. 4. ac timing tests have v il = 0.4v and v ih = 2.4v with the timing referenced to the 1.4v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown. specific tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0v. 5. if clock rising time is longer than 1 ns, a time (t t /2 -0.5) ns has to be added to this parameter. 6. rated at 1.5v 7. if t t is longer than 1 ns, a time (t t -1) ns has to be added to this parameter. 8. any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to wake-up the device. 9. self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied once the self refresh exit command is registered. 10. referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. t dal is equivalent to t dpl + t rp . 1.4v 1.4v tsetup thold tac tac tlz toh thz clock input output 50 pf i/o z=50 ohm + 1.4 v 50 ohm 2.4v 0.4v t t tcl tch i/o measurement conditions for tac and toh 50 pf
10 V437216C04VDTG-75 rev. 1.2 july 2001 mosel vitelic V437216C04VDTG-75 package diagram l-dim-168-30 sdram dimm module package 127.35 133.37 42.18 d 63.68 3.0 1.27 0.100 all measurements in mm 43.15 11011 4041 84 85 94 95 124 125 168 17.80 b a 6.35 2.26 radius 1.27 + 0.10 detail a 3.125 4.45 2.0 6.35 3.175 detail b 3.125 2.0 1.0 0.05 1.27 detail c 2.50 0.2 0.15 4.0 tolerances: (0.13) unless otherwise specified. (4.0 max)
mosel vitelic V437216C04VDTG-75 11 V437216C04VDTG-75 rev. 1.2 july 2001 label information c l = 3 (clk) t rcd = 3 (clk) t rp = 3 (clk) t ac = 5.4 ns 333 r registered dimm pc133 54 jedec spd revision 2.0 2 V437216C04VDTG-75 pc133r-333-542-a taiwan xxxx-xxxxxxx a gerber file intel pc100 x 4 based -- - mosel vitelic part number dimm manufacture date code trace code criteria of pc100 or pc133 (refer to mvi datasheet)
mosel vitelic worldwide offices V437216C04VDTG-75 ? copyright 2001, mosel vitelic inc. 7/01 printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u.s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 03-3537-1400 fax: 03-3537-1402 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 44-1698-748515 fax: 44-1698-748516 germany (continental europe & israel) benzstrasse 32 71083 herrenberg germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central, northeastern & southeastern 604 fieldwood circle richardson, tx 75081 phone: 214-826-6176 fax: 214-828-9754

▲Up To Search▲

Price & Availability of V437216C04VDTG-75

	To Download V437216C04VDTG-75 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .